Significant progress has been made in the research and development of next generation semiconductor devices. JFET is promising for high power and high temperature applications. Vertical JFET on bulk GaN with vertical drift region has been demonstrated. However, there are several issues. One issue is that source and p-type block layer typically not Ohmic. It would affect switch behavior and long-term reliability. The second issue is that regrowth of lateral and vertical channel often is high resistive due to counter doping during the regrowth.
Both issues affect the reliability and performance of the JFET. Improvement and enhancement are desired for JFET for an improved Ohmic contact and less resistive lateral channel layer.